Automated Generation of Instruction Set Simulator from Specification

Abstract—We present here an architecture compiler, namely a software that takes as input the description of a processor architecture as it is available from the vendors on their web site, and generates an instruction set simulator for that processor, which can be readily integrated into a simulation framework. This architecture compiler extracts relevant information from the .pdf file, translated into an XML specification. After further XML transformations, the C++ code of the simulator is finally generated. The paper details the approach and the results for the ARM Version 7 processor, which is suitable for other architectures as well.

Index Terms—Instruction set simulator, computer architecture, hardware simulation, compiler.

Shenpeng Liu and Fei He are with Tsinghua University, China (e-mail: werewolflsp@gmail.com, hefei@tsinghua.edu.cn).
Vania Joloboff is with East China Normal University, China (e-mail: vania.joloboff@inria.fr).

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Cite:Shengpeng Liu, Fei He, and Vania Joloboff, "Automated Generation of Instruction Set Simulator from Specification," Lecture Notes on Software Engineering vol. 4, no. 3, pp. 238-241, 2016.