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General Information
    • ISSN: 2301-3559
    • Frequency: Quarterly
    • DOI: 10.18178/LNSE
    • Editor-in-Chief: Prof. Jemal Antidze
    • Executive Editor: Ms. Nina Lee
    • Abstracting/ Indexing: EI (INSPEC, IET), Electronic Journals Library,  Ulrich's Periodicals Directory, International Computer Science Digital Library (ICSDL), ProQuest and Google Scholar.
    • E-mail: lnse@ejournal.net
Prof. Jemal Antidze
I. Vekua Scientific Institute of Applied Mathematics
Tbilisi State University, Georgia
I'm happy to take on the position of editor in chief of LNSE. We encourage authors to submit papers concerning any branch of Software Engineering.

LNSE 2016 Vol.4(3): 238-241 ISSN: 2301-3559
DOI: 10.18178 /LNSE.2016.V4.257

Automated Generation of Instruction Set Simulator from Specification

Shengpeng Liu, Fei He, and Vania Joloboff
Abstract—We present here an architecture compiler, namely a software that takes as input the description of a processor architecture as it is available from the vendors on their web site, and generates an instruction set simulator for that processor, which can be readily integrated into a simulation framework. This architecture compiler extracts relevant information from the .pdf file, translated into an XML specification. After further XML transformations, the C++ code of the simulator is finally generated. The paper details the approach and the results for the ARM Version 7 processor, which is suitable for other architectures as well.

Index Terms—Instruction set simulator, computer architecture, hardware simulation, compiler.

Shenpeng Liu and Fei He are with Tsinghua University, China (e-mail: werewolflsp@gmail.com, hefei@tsinghua.edu.cn).
Vania Joloboff is with East China Normal University, China (e-mail: vania.joloboff@inria.fr).


Cite:Shengpeng Liu, Fei He, and Vania Joloboff, "Automated Generation of Instruction Set Simulator from Specification," Lecture Notes on Software Engineering vol. 4, no. 3, pp. 238-241, 2016.

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